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CMOS SyncFIFOTM 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
Integrated Device Technology, Inc.
IDT72205LB IDT72215LB IDT72225LB IDT72235LB IDT72245LB
FEATURES:
* * * * * * * * * * * * * * * 256 x 18-bit organization array (72205LB) 512 x 18-bit organization array (72215LB) 1024 x 18-bit organization array (72225LB) 2048 x 18-bit organization array (72235LB) 4096 x 18-bit organization array (72245LB) 15 ns read/write cycle time Easily expandable in depth and width Read and write clocks can be asynchronous or coincident Dual-Port zero fall-through time architecture Programmable almost-empty and almost-full flags Empty and Full flags signal FIFO status Half-Full flag capability in a single device configuration Output enable puts output data bus in high-impedance state High-performance submicron CMOS technology Available in a 64-lead thin quad flatpack (TQFP/STQFP), pin grid array (PGA), and plastic leaded chip carrier (PLCC) Military product compliant to MIL-STD-883, Class B Industrial temperature range (-40OC to +85OC) is available, tested to military electrical specifications
* *
DESCRIPTION:
The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering needs, such
as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Both FIFOs have 18-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and a data input enable pin (WEN). Data is read into the synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and another enable pin (REN). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output. The synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF), and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available when the FIFO is used in a single device configuration. The IDT72205LB/72215LB/72225LB/72235LB/72245LB are depth expandable using a daisy-chain technique. The XI and XO pins are used to expand the FIFOs. In depth expansion configuration, FL is grounded on the first device and set to HIGH for all other devices in the daisy chain. The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated using IDT's high-speed submicron CMOS technology. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
WEN
WCLK D0-D17
LD
OFFSET REGISTER
INPUT REGISTER
WRITE CONTROL LOGIC
WRITE POINTER
FL WXI (HF)/WXO RXI RXO RS
* * RAM ARRAY 256 x 18, 512 x 18 1024 x 18, 2048 x 18 4096 x 18 * *
FLAG LOGIC
FF PAF EF PAE HF/(WXO)
READ POINTER READ CONTROL LOGIC
EXPANSION LOGIC OUTPUT REGISTER RESET LOGIC
OE
Q0-Q17
RCLK
REN
2766 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2766/7
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
11 VCC Q3 GND Q0 Q2 Q1
10 GND Q4 09 08 Q6 Q7 Q5 VCC
WXO/ RXI VCC WEN FL HF RXO FF PAF WXI WCLK PAE
D2 D4 D6 G68-1
D0 D1 D3 D5
07 GND Q8 06 05 Q10 Q9
GND D7 VCC D8
Q11 VCC Pin 1 Designator
04 GND Q12 03 02 01 A Q14 Q13
D10
D9
D12 D11
VCC Q15 Q16 VCC GND GND Q17 B C
RS LD OE REN
F G
RCLK
D17 D14
D13
EF
D
VCC E
GND D16 D15 H J K L
PGA TOP VIEW
2766 drw 02
D15 D16 D17 GND RCLK
VCC GND
D14 D13 D12 D11 D10 D9 VCC D8 GND D7 D6 D5 D4 D3 D2 D1 D0
98765432 68 67 66 65 64 63 62 61 10 60 1 11 59 12 58 13 57 14 56 15 55 16 54 17 53 J68-1 18 52 19 51 20 50 49 21 48 22 47 23 46 24 45 25 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
VCC Q17 Q16 GND Q15
VCC Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 VCC Q6 Q5 GND Q4
2766 drw 03
REN LD OE RS
VCC
5.16
WEN WXI
WCLK
PAF RXI FF WXO/HF RXO
PLCC TOP VIEW
Q0 Q1 GND Q2 Q3 VCC
PAE FL
EF
2
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
RCLK GND GND
REN LD OE RS
GND
VCC
PIN 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 PN 64-1 41 8 PP64-1 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 Q6 Q5 GND Q4 VCC
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PAF RXI FF WXO/HF RXO
PAE FL
WEN WXI
VCC
GND
Q0
Q1
WCLK
Q2
Q3
VCC
D17
Q17
Q16
D16
Q15
EF
2766 drw 04
TQFP/STQFP TOP VIEW NOTE: 1. For information on the flatpack (F68-1), contact factory.
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol D0-D17 Name Data Inputs Reset I/O I I Data inputs for a 18-bit bus. When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up. When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full. When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW. Description
RS
WCLK
Write Clock Write Enable
I I
WEN
RCLK
Read Clock Read Enable
I I
When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty. When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the EF is LOW. When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state.
REN OE LD
Output Enable Load
I I
FL WXI RXI EF PAE PAF FF WXO/HF RXO
Q0-Q17 VCC GND
First Load
I
In the single device or width expansion configuration, FL is grounded. In the depth expansion configuration, FL is grounded on the first device (first load device) and set to HIGH for all other devices in the daisy chain. In the single device or width expansion configuration, WXI is grounded. In the depth expansion configuration, WXI is connected to WXO (Write Expansion Out) of the previous device.
When LD is LOW, data on the inputs D0-D11 is written to the offset and depth registers on the LOW-to-HIGH transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0-Q11 is read from the offset and depth registers on the LOW-toHIGH transition of the RCLK, when REN is LOW.
Write Expansion Input Read Expansion Input Empty Flag
I
I
In the single device or width expansion configuration, RXI is grounded. In the depth expansion configuration, RXI is connected to RXO (Read Expansion Out) of the previous device. When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO. The default offset at reset is 31 from empty for 72205LB, 63 from empty for 72215LB, and 127 from empty for 72225LB/72235LB/72245LB.
O
Programmable O Almost-Empty Flag Programmable O
When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The default offset at reset is 31 from full for 72205LB, 63 from full for 72215LB, and 127 from full for 72225LB/72235LB/72245LB. When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to WXI of the next device when the last location in the FIFO is written.
Full Flag Write Expansion Out/Half-Full Flag Read Expansion Out Data Outputs Power Ground
O O
O O
In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last location in the FIFO is read. Data outputs for a 18-bit bus.
Eight +5V power supply pins for the PLCC and PGA, five pins for the TQFP. Eight ground pins for the PLCC and PGA, seven pins for the TQFP.
2766 tbl 01
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TA TBIAS TSTG IOUT Rating Commercial MIilitary -0.5 to +7.0 -55 to +125 -65 to +135 -65 to +155 50 Unit V C Terminal Voltage -0.5 to +7.0 with respect to GND Operating Temperature 0 to +70
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCCM VCCC Parameter Military Supply Voltage Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input High Voltage Military Input Low Voltage Commercial & Military Min. 4.5 4.5 0 2.0 2.2 -- Typ. 5.0 5.0 0 -- -- -- Max. 5.5 5.5 0 -- -- 0.8 Unit V V V V V V
Temperature Under -55 to +125 Bias Storage Temperature DC Output Current -55 to +125 50
C GND C mA VIH VIH VIL(1)
NOTE: 2766 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maimum rating conditions for extended
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
2766 tbl 03
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to +70C; Military: VCC = 5V 10%, TA = -55C to +125C)
IDT72205LB IDT72215LB IDT72225LB Commercial tCLK = 15, 20, 25, 35, 50ns Symbol ILI(1) ILO(2) VOH VOL ICC1(3) ICC2(3) Parameter Input Leakage Current (any input) Output Leakage Current Output Logic "1" Voltage, IOH = -2 mA Output Logic "0" Voltage, IOL = 8 mA Active Power Supply Current Average Standby Current (All Input = VCC - 0.2V, except RCLK and WCLK which are free-running) Min. -1 -10 2.4 -- -- -- Typ. -- -- -- -- -- -- Max. 1 10 -- 0.4 200 70 IDT72205LB IDT72215LB IDT72225LB Military tCLK = 25, 35, 50ns Min. -10 -10 2.4 -- -- -- Typ. -- -- -- -- -- -- Max. 10 10 -- 0.4 250 85 Unit A A V V mA mA
IDT72235LB IDT72245LB Commercial tCLK = 15, 20, 25, 35, 50ns Symbol ILI
(1) (2)
IDT72235LB IDT72245LB Military tCLK = 25, 35, 50ns Min. -10 -10 2.4 -- -- -- Typ. -- -- -- -- -- -- Max. 10 10 -- 0.4 250 85 Unit A A V V mA mA
2766 tbl 04
Parameter Input Leakage Current (any input) Output Leakage Current Output Logic "1" Voltage, IOH = -2 mA Output Logic "0" Voltage, IOL = 8 mA Active Power Supply Current Average Standby Current (All Input = VCC - 0.2V, except RCLK and WCLK which are free-running)
Min. -1 -10 2.4 -- -- --
Typ. -- -- -- -- -- --
Max. 1 10 -- 0.4 200 70
ILO
VOH VOL ICC1 ICC2
(4) (4)
NOTES: 1. Measurements with 0.4 VIN VCC. 2. OE VIH, 0.4 VOUT VCC. 3 & 4. Tested at f = 20MHz with outputs unloaded. (3) Typical Icc1 = 60 + (fCLK*0.57/MHz) + (fCLK*CL*0.02/MHz-pF) mA (4 ) Typical Icc1 = 80 + (fCLK + 0.73/MHz) + (fCLK*CL*0.02/MHz-pF) mA fCLK = 1/tCLK, CL = external capacitive load (30 pF typical)
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN
(2)
Parameter(1) Input Capacitance Output Capacitance
Conditions VIN = 0V VOUT = 0V
Max. 10 10
Unit pF pF
COUT(1,2)
NOTES: 1. With output deselected, (OE = HIGH). 2. Characterized values, not currently tested.
2766 tbl 05
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to +70C; Military: VCC = 5V 10%, TA = -55C to +125C)
Commercial 72205LB15 72205LB20 72215LB15 72215LB20 72225LB15 72225LB20 72235LB15 72235LB20 72245LB15 72245LB20 Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAF tPAE tHF tXO tXI tXIS tSKEW1 tSKEW2 Parameter Clock Cycle Frequency Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width(1) Reset Set-up Time Reset Recovery Time Reset to Flag and Output Time Output Enable to Output in Low-Z(2) Output Enable to Output Valid Output Enable to Output in High-Z(2) Write Clock to Full Flag Read Clock to Empty Flag Clock to Programmable Almost-Full Flag Clock to Programmable Almost-Empty Flag Clock to Half-Full Flag Clock to Expansion Out Expansion In Pulse Width Expansion In Set-Up Time Skew time between Read Clock & Write Clock for Full Flag Skew time between Read Clock & Write Clock for Empty Flag Min. Max. -- 2 15 6.5 6.5 4 1 4 1 15 10 10 -- 0 -- 1 -- -- -- -- -- -- 6.5 5 10 10 66.7 10 -- -- -- -- -- -- -- -- -- -- 35 -- 8 8 10 10 28 28 28 10 -- -- -- -- Min. -- 2 20 8 8 5 1 5 1 20 12 12 -- 0 -- 1 -- -- -- -- -- -- 8 8 14 14 Max. 50 12 -- -- -- -- -- -- -- -- -- -- 35 -- 9 9 12 12 30 30 30 12 -- -- -- -- Commercial and Military 72205LB25 72205LB35 72205LB50 72215LB25 72215LB35 72215LB50 72225LB25 72225LB35 72225LB50 72235LB25 72235LB35 72235LB50 72245LB25 72245LB35 72245LB50 Min. -- 3 25 10 10 6 1 6 1 25 15 15 -- 0 -- 1 -- -- -- -- -- -- 10 10 16 16 Max. 40 15 -- -- -- -- -- -- -- -- -- -- 40 -- 12 12 15 15 35 35 35 15 -- -- -- -- Min. -- 3 35 14 14 7 2 7 2 35 20 20 -- 0 -- 1 -- -- -- -- -- -- 14 15 18 18 Max. Min. 28.6 20 -- -- -- -- -- -- -- -- -- -- 45 -- 15 15 20 20 40 40 40 20 -- -- -- -- -- 3 50 20 20 10 2 10 2 50 30 30 -- 0 -- 1 -- -- -- -- -- -- 20 20 20 20 Max. 20 25 -- -- -- -- -- -- -- -- -- -- 50 -- 20 20 30 30 40 40 40 30 -- -- -- -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2766 tbl 06
NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested.
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1
2766 tbl 07
5V
1.1K D.U.T. 680 30pF*
2766 drw 05
Figure 1. Output Load * Includes jig and scope capacitances.
SIGNAL DESCRIPTIONS:
INPUTS: DATA IN (D0 - D17) Data inputs for 18-bit wide data. CONTROLS: RESET (RS RS) Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. The Full Flag (FF), Half-Full Flag (HF), and Programmable AlmostFull Flag (PAF) will be reset to HIGH after tRSF. The Empty Flag (EF) and Programmable Almost-Empty Flag (PAE) will be reset to LOW after tRSF. During reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. WRITE CLOCK (WCLK) A write cycle is initiated on the LOW-to-HIGH transition of the write clock (WCLK). Data set-up and hold times must be met with respect to the LOW-to-HIGH transition of the write clock (WCLK). The write and read clocks can be asynchronous or coincident. WRITE ENABLE (WEN WEN) When Write Enable (WEN) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation. When WEN is HIGH, the input register holds the previous data and no new data is loaded into the FIFO. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the FF will go HIGH after tWFF allowing a write to begin. WEN is ignored when the FIFO is full. READ CLOCK (RCLK) Data can be read on the outputs on the LOW-to-HIGH transition of the read clock (RCLK), when Output Enable (OE) is set LOW.
The write and read clocks can be asynchronous or coincident. READ ENABLE (REN REN) When Read Enable (REN) is LOW, data is loaded from the RAM array to the output register on the LOW-to-HIGH transition of the read clock (RCLK). When REN is HIGH, the output register holds the previous data and no new data is loaded into the register. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. Once a write is performed, the EF will go HIGH after tREF and a read can begin. REN is ignored when the FIFO is empty. OUTPUT ENABLE (OE OE) When Output Enable (OE) is enabled (LOW), the parallel output buffers receive data from the output register. When OE is disabled (HIGH), the Q output data bus is in a highimpedance state. LOAD (LD LD) The IDT72205LB/72215LB/72225LB/72235LB/72245LB devices contain two 12-bit offset registers with data on the inputs, or read on the outputs. When the Load (LD) pin is set LOW and WEN is set LOW, data on the inputs D0-D11 is written into the Empty offset register on the first LOW-to-HIGH transition of the write clock (WCLK). When the LD pin and
LD 0 WEN 0 WCLK(1) Selection Writing to offset registers: Empty Offset Full Offset 0 1 1 1 0 1 No Operation Write Into FIFO No Operation
NOTE: 2766 tbl 08 1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK. Figure 2. Write Offset Register
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(WEN) are held LOW then data is written into the Full offset register on the second LOW-to-HIGH transition of the write clock (WCLK). The third transition of the write clock (WCLK) again writes to the Empty offset register. However, writing all offset registers does not have to occur at one time. One or two offset registers can be written and then by bringing the LD pin HIGH, the FIFO is returned to normal read/write operation. When the LD pin is set LOW, and WEN is LOW, the next offset register in sequence is written. When the LD pin is LOW and WEN is HIGH, the WCLK input is disabled; then a signal at this input can neither increment the write offset register pointer, nor execute a write. The contents of the offset registers can be read on the output lines when the LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-to-HIGH transition of the read clock (RCLK). The act of reading the control registers employs a dedicated read offset register pointer. (The read and write pointers operate independently). A read and a write should not be performed simultaneously to the offset registers.First Load (FL) First Load (FL) is grounded to indicate operation in the Single Device or Width Expansion mode. In the Depth Expansion configuration, FL is grounded to indicate it is the first device loaded and is set to HIGH for all other devices in the daisy chain. (See Operating Configurations for further details.) WRITE EXPANSION INPUT (WXI WXI) This is a dual purpose pin. Write Expansion In (WXI) is grounded to indicate operation in the Single Device or Width
Expansion mode. WXI is connected to Write Expansion Out (WXO) of the previous device in the Depth Expansion or Daisy Chain mode. READ EXPANSION INPUT (RXI) This is a dual purpose pin. Read Expansion In (RXI) is grounded to indicate operation in the Single Device or Width Expansion mode. RXI is connected to Read Expansion Out (RXO) of the previous device in the Depth Expansion or Daisy Chain mode.
17 11 EMPTY OFFSET REGISTER DEFAULT VALUE 001FH (72205) 003FH (72215): 007FH (72225/72235/72245) 0
17
11 FULL OFFSET REGISTER DEFAULT VALUE 001FH (72205) 003FH (72215): 007FH (72225/72235/72245)
0
NOTE: 2766 drw 06 1. Any bits of the offset register not being programmed should be set to zero. Figure 3. Offset Register Location and Default Values
TABLE I -- STATUS FLAGS
Number of Words in FIFO 72205 0 1 to n(1) (n + 1) to 128 (256-m)(2) to 255 256 72215 0 1 to n(1) (n + 1) to 256 (512-m)(2) to 511 512 72225 0 1 to n(1) (n + 1) to 512 (1024-m)(2) to 1023 1024 72235 0 1 to n(1) (n + 1) to 1024 (2048-m)(2) to 2047 2048 72245 0 1 to n(1) (n + 1) to 2048 (4096-m)(2) to 4095 4096
FF PAF HF PAE EF
H H H H L H H H H L L H H H L L L L L H H H H L H H H H H
129 to (256-(m+1)) 257 to (512-(m+1)) 513 to (1024-(m+1)) 1025 to (2048-(m+1)) 2049 to (4096-(m+1)) H
NOTES: 1. n = Empty Offset (Default Values : 72205 n=31, 72215 n = 63, 72225/72235/72245 n = 127) 2. m = Full Offset (Default Values : 72205 n=31, 72215 n = 63, 72225/72235/72245 n = 127)
2766 tbl 09
OUTPUTS: FULL FLAG (FF FF) The Full Flag (FF) will go LOW, inhibiting further write operation, indicating that the device is full. If no reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 256 writes for the IDT72205LB, 512 writes for the IDT72215LB, 1024 writes for the IDT72225LB, 2048 writes for the IDT72235LB and 4096 writes for the IDT72245LB. The Full Flag (FF) is updated on the LOW-to-HIGH transition of the write clock (WCLK).
EMPTY FLAG (EF) The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. The EF is updated on the LOW-to-HIGH transition the read clock (RCLK). PROGRAMMABLE ALMOST-FULL FLAG (PAF PAF) The Programmable Almost-Full Flag (PAF) will go LOW when FIFO reaches the Almost-Full condition. If no reads are performed after Reset (RS), the PAF will go LOW after (256-
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
m) writes for the IDT72205LB, (512-m) writes for the IDT72215LB, (1024-m) writes for the IDT72225LB, (2048-m) writes for the IDT72235LB and (4096-m) writes for the IDT72245LB. The offset "m" is defined in the FULL offset register. If there is no Full offset specified, the PAF will be LOW when the device is 31 away from completely full for 72205LB, 63 away from completely full for 72215LB, and 127 away from completely full for 72225LB/72235LB/72245LB. The PAF is asserted LOW on the LOW-to-HIGH transition of the write clock (WCLK). PAF is reset to HIGH on the LOWto-HIGH transition of the read clock (RCLK). Thus PAF is asychronous. PROGRAMMABLE ALMOST-EMPTY FLAG (PAE PAE) The Programmable Almost-Empty Flag (PAE) will go LOW when the read pointer is "n+1" locations less than the write pointer. The offset "n" is defined in the EMPTY offset register. If there is no Empty offset specified, the Programmable Almost Empty Flag (PAE) will be LOW when the device is 31 away from completely empty for 72205LB, 63 away from completely empty for 72215LB, and 127 away from completely empty for 72225LB/72235LB/72245LB. The PAE is asserted LOW on the LOW-to-HIGH transition of the read clock (RCLK). PAE is reset to HIGH on the LOWto-HIGH transition of the write clock (WCLK). Thus PAF is asychronous.
WRITE EXPANSION OUT/HALF-FULL FLAG (WXO HF) WXO/HF This is a dual-purpose output. In the Single Device and Width Expansion mode, when Write Expansion In (WXI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled, and at the LOW-to-HIGH transition of the next write cycle, the Half-Full Flag goes LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset to HIGH by the LOW-to-HIGH transition of the read clock (RCLK). The HF is asychronous. In the Depth Expansion or Daisy Chain mode, WXI is connected to WXO of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse when the previous device writes to the last location of memory. READ EXPANSION OUT (RXO RXO) In the Depth Expansion or Daisy Chain configuration, Read Expansion In (RXI) is connected to Read Expansion Out (RXO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse when the previous device reads from the last location of memory. DATA OUTPUTS (Q0-Q17) Q0-Q17 are data outputs for 18-bit wide data.
RS REN, WEN, LD
t RS
t RSR
t RSF
EF , PAE FF, PAF,HF
Q0 - Q17
NOTES: 1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1. 2. The clocks (RCLK, WCLK) can be free-running during reset. Figure 5. Reset Timing(2)
t RSF
t RSF
OE = 1(1) OE = 0
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t CLK t CLKH WCLK t DS D0 - D17
DATA IN VALID
t CLKL
t DH
t ENS
t ENH
WEN
NO OPERATION
t WFF
t WFF
FF
t SKEW1(1)
RCLK
REN
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NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. Figure 6. Write Cycle Timing
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t CLK t CLKH RCLK t t ENH t CLKL
ENS
NO OPERATION
REN
t REF t REF
EF
tA Q0 - Q17 t OLZ
VALID DATA
t OHZ
OE
t OE
t SKEW2(1) WCLK
WEN
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NOTE: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge. Figure 7. Read Cycle Timing
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK t DS
D0 - D17
D0 (first valid write)
D1
D2
D3
D4
t ENS
WEN
t FRL t SKEW2 RCLK
(1)
EF
t REF
REN
tA Q0 - Q17 t OLZ t
OE
tA D0 D1
OE
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NOTES: 1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). 2. The first word is available the cycle after EF goes HIGH, always. Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
NO WRITE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NO WRITE
WCLK t SKEW1 D0 - D17
(1)
t DS
(1)
t SKEW1 DATA WRITE
t DS DATA WRITE
t WFF
t WFF
t WFF
FF
WEN
RCLK t ENH t ENS t ENS t ENH
REN
OE
LOW tA tA DATA READ NEXT DATA READ
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Q0 - Q17
DATA IN OUTPUT REGISTER
Figure 9. Full Flag Timing NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
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13
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK tDS tDS
D0 - D17 tENS
DATA WRITE 1 tENH tENS
DATA WRITE 2 tENH
WEN
tFRL tSKEW2 RCLK
(1)
tFRL tSKEW2
(1)
tREF
tREF
EF
REN
OE
LOW
tA Q0 - Q17 DATA IN OUTPUT REGISTER DATA READ
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Figure 10. Empty Flag Timing NOTE: 1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW2. or tCLK + tSKEW2. The Latency Timing apply only at the Empty Boundary (EF = LOW).
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14
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLK tCLKH WCLK tENS LD tENS tENH tCLKL
WEN tDS tDH PAE OFFSET D0-D15 PAE OFFSET PAF OFFSET D0-D11
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Figure 11. Write Programmable Registers
tCLK tCLKH RCLK tENS LD tENS tENH tCLKL
REN
tA Q0-Q15 UNKNOWN PAE OFFSET PAF OFFSET
PAE OFFSET
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Figure 12. Read Programmable Registers
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15
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLKH WCLK tENS WEN
tCLKL
tENH
tPAE PAE n + 1 words in FIFO tPAE RCLK tENS REN
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n words in FIFO
NOTE: 1. PAE is offset = n. Number of data words written into FIFO already = n. Figure 13. Programmable Almost Empty Flag Timing
tCLKH WCLK (1) tENS WEN
tCLKL
tENH
tPAF PAF Full - m words in FIFO(2) tPAF RCLK tENS REN
2766 drw 16
Full - m + 1 words in FIFO(3)
NOTES: 1. PAF offset = m. Number of data words written into FIFO already = 256 - m + 1 for the IDT72205B, 512 - m + 1 for the IDT72215B, 1024 - m + 1 for the IDT72225B, 2048 - m + 1 for the IDT72235B and 4096 - m +1 for the IDT72245B. 2. 256 - m words in IDT72205B, 512 - m words in IDT72215B, 1024 - m words in IDT72225B, 2048 - m words in IDT72235B and 4096 - m words in IDT72245B. 3. 256 - m + 1 words in IDT72205B, 512 - m + 1 words in IDT72215B, 1024 - m + 1 words in IDT72225B, 2048 - m + 1 words in IDT72235B and 4096 - m + 1 words in IDT72245B. Figure 14. Programmable Almost-Full Flag Timing
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16
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLKH WCLK tENS WEN
tCLKL
tENH
tHF HF Half Full or Less Half Full + 1 or More tHF RCLK tENS REN
2766 drw 17
Half Full or Less
Figure 15. Half-Full Flag Timing
t CLKH WCLK Note 1 t XO t XO
WXO
t ENS
WEN
NOTE: 1. Write to Last Physical Location. Figure 16. Write Expansion Out Timing
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t CLKH RCLK Note 1 t XO t XO
RXO
t ENS
REN
NOTE: 1. Read from Last Physical Location. Figure 17. Read Expansion Out Timing
2766 drw 19
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t XI
WXI
t XIS WCLK
2766 drw 20
Figure 18. Write Expansion In Timing
t XI
RXI
t XIS RCLK
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Figure 19. Read Expansion In Timing
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION A single IDT72205LB/72215LB/72225LB/72235LB/ 72245LB may be used when the application requirements are for 256/512/1024/2048/4096 words or less. The IDT72205LB/ 72215LB/72225LB/72235LB/72245LB are in a single Device Configuration when the Write Exansion In (WXI), Read Expansion In (RXI), and First Load (FL) control inputs are grounded (Figure 20).
RESET (RS) WRITE CLOCK (WCLK) WRITE ENABLE (WEN) LOAD (LD) DATA IN (D0 - D17) FULL FLAG (FF) PROGRAMMABLE (PAE) HALF-FULL FLAG (HF) IDT 72205LB/ 72215LB/ 72225LB/ 72235LB/ 72245LB READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) DATA OUT (Q0 - Q17) EMPTY FLAG (EF) PROGRAMMABLE (PAF)
FIRST LOAD (FL)
READ EXPANSION IN (RXI) WRITE EXPANSION IN (WXI)
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Figure 20. Block Diagram of Single 256 x 18/512 x 18/1024 x 18/2048 x 18/4096 x 18 Synchronous FIFO
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one device. The exceptions are the Empty Flag and Full Flag. Because of variations in skew between RCLK and WCLK, it is possible for flag assertion and deassertion to vary by one cycle between FIFOs. To avoid
problems the user must create composite flags by ANDing the Empty Flags of every FIFO, and separately ANDing all Full Flags. Figure 21 demonstrates a 36-word width by using two IDT72205B/72215B/72225B/72235B/72245Bs. Any word width can be attained by adding additional IDT72205B/72215B/ 72225B/72235B/72245Bs. Please see the Application Note AN-83.
RESET (RS)
RESET (RS)
DATA IN (D)
36
18
18 READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) 72205LB/ 72215LB/ 72225LB/ 72235LB/ 72245LB 72205LB/ 72215LB/ 72225LB/ 72235LB/ 72245LB PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK) WRITE ENABLE (WEN) LOAD (LD) PROGRAMMABLE (PAE) HALF FULL FLAG (HF)
EMPTY FLAG (EF)
FF
FULL FLAG (FF)
EF
18
FF
EF
18 DATA OUT (Q) 36
FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI)
2766 drw 23
NOTE: 1. Do not connect any output control signals directly together. Figure 21. Block Diagram of 256 x 36/512 x 36/1024 x 36/2048 x 36/4096 x 36 Synchronous FIFO Memory Used in a Width Expansion Configuration
DEPTH EXPANSION CONFIGURATION (WITH PROGRAMMABLE FLAGS) The IDT72205LB/72215LB/72225LB/72235LB/72245LB can easily be adapted to applications requiring more than 256/ 512/1024/2048/4096 words of buffering. Figure 22 shows Depth Expansion using three IDT72205LB/72215LB/72225LB/ 72235LB/72245LBs. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device. See Figure 24.
4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device. See Figure 24. 5. All Load (LD) pins are tied together. 6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together every respective flags for monitoring. The composite PAE and PAF flags are not precise.
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WXO RXO
WCLK
Vcc
*
IDT 72205LB/ 72215LB/ 72225LB/ Dn 72235LB/ Qn 72245LB
WEN RS LD
RCLK
REN OE
FL FF PAF EF PAE WXI RXI
*
WXO RXO
*
*
*
WEN RS LD
WCLK RCLK
REN OE
*
*
*
DATA IN Vcc
*
IDT 72205LB/ 72215LB/ Dn 72225LB/ Qn 72235LB/ 72245LB
*
DATA OUT
FL FF PAF
EF PAE WXI RXI
WRITE CLOCK WRITE ENABLE RESET LOAD
* * * *
WCLK
WXO RXO
RCLK
WEN RS
Dn
* * *
READ CLOCK READ ENABLE OUTPUT ENABLE
REN OE
FF PAF
FIRST LOAD (FL)
IDT Qn 72205LB/ LD 72215LB/ 72225LB/ 72235LB/ 72245LB
FF
EF PAE
EF
PAE PAF WXI RXI
2766 drw 24
Figure 22. Block Diagram of 768 x 18/1536 x 18/3072 x 18/6144 x 18/12288 x 18 Synchronous FIFO Memory With Programmable Flags used in Depth Expansion Configuration
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type X Power XX Speed X Package X Process / Temperature Range BLANK B Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B Plastic Leaded Chip Carrier Pin Grid Array Thin Plastic Quad Flatpack Slim Thin Plastic Quad Flatpack Clock Cycle Time (tCLK) Speed in Nanoseconds
J G PF TF
15 Com'l Only 20 Com'l Only 25 35 50 LB 72205 72215 72225 72235 72245
Low Power 256 x 18 Synchronous FIFO 512 x 18 Synchronous FIFO 1024 x 18 Synchronous FIFO 2048 x 18 Synchronous FIFO 4096 x 18 Synchronous FIFO
2766 drw 25
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